Centre for Excellence in Applied Research in FPGA towards enabling a truly Open Source Hardware and Software Ecosystem.
Primary objectives of CoE are , but not limited to:
- Create HW and SW infrastructure to enable development and verification of custom RISC V CPU.
- Create RISC-V Cores based evaluation HW for use in LoRaWAN Applications.
- Promote Open Source Hardware at Silicon Level.
Drive the adoption of Open Hardware among startups.
- Evaluation HW from Olimex,MCCI etc based on Lattice ICE FPGA's .
- Industrial boards such as Digilient Arty A7 100 T
- Test Bench Equipment.
- Software tools for PNR Synthesis
- Tools for Verilog development workflow
- Tools for verification( Pre-Silicon).